Intel Core Microarchitecture - Page 2

..:: Wide Dynamic Execution ::..

Dynamic Execution is the term Intel uses to describe their various methods of processing instructions, such as out-of-order and speculative execution. Intel Core microarchitecture improves upon the NetBurst and Mobile microarchitectures by employing Wide Dynamic Execution. This technology allows for more instructions to be sent to the execution units per clock cycle than with previous generation microarchitectures.

The first method of improving instruction delivery is with widened execution cores. With the Core microarchitecture, Intel has moved to four-wide execution cores. This means that, with the Core microarchitecture, each processing core can fetch, dispatch, execute and return up to four instructions at once. The older microarchitectures were only capable of working with up to three instructions at once.

A second method of improving instruction delivery is with Macrofusion. In previous microarchitectures, all incoming instructions were decoded and executed individually. Macrofusion allows for common instruction pairs to be combined into a single micro-op during the decoding process. This allows for two instructions to effectively be executed as one micro-op. This allows for an increase in the potential number of instructions that can be executed in a given time, as well as the time it takes to complete the series of instructions. In order to accompany this new capability, the ALU’s have had support added for single cycle execution of these combined micro-ops. This technology improves IPC as well as energy efficiency by doing more in a shorter time, requiring less power.

Finally, one of the key technologies from the Pentium M microarchitecture that has made its way into the Core microarchitecture is that of micro-op fusion. Program instructions, called macro-ops, are broken down into micro-ops before being sent to the processor pipeline. Micro-op fusion combines micro-ops from the same macro-op to reduce the number of micro-ops that need to be processed. This allows for improved scheduling and low power performance. Intel claims that micro-op fusion can reduce the number of micro-ops processed by the out-of-order execution engine by up to ten percent. With Intel’s Core microarchitecture, the number of micro-ops that can be “fused” has been increased.

Each of these innovations allows for an increase in the instructions executed per clock cycle, as well as a reduction in the amount of power used for processing. In the graphic below, we see each of these features laid out in a flow chart. Given that the Intel Core microarchitecture processors feature at least two processing cores, each processor has the capability to work with up to eight instructions simultaneously, sixteen in the case of the upcoming quad core processors.