Motherboard Design Process - Page 2

..:: Design Simulations ::..

The beginning stages of the actual motherboard design process starts out by running several complex simulations on either third party software, or in-house software depending on the manufacturer. These simulations are very important as they give the motherboard designers an overlay about proper trace routing, an especially important factor for the various system buses. These simulations determine the impendence of the traces and are used to establish the minimum and maximum length and width of the traces, along with the minimum allowable spacing between the traces. These factors all come into play for problems such as signal degradation, ground bounce, EMI, etc.

Typically, today’s printed circuit board designs aim for a trace impedance of roughly 60 Ohms, sometimes higher or lower depending on which bus the trace is going to be part of. A “normal” trace width that can be used for one of these high speed bus connections is roughly 5/1000 of an inch. When a motherboard designer starts work with the printed circuit board design, they’ll work closely with the printed circuit board manufacturer in order to determine the optimal build, or “stack-up” of the various layers that will make up the motherboard. Motherboards today are designed with multiple layers in mind, each being responsible for a given task such as signaling, ground, or power distribution. Each of these layers is separated from each other by a “prepreg” layer which helps in determining the “static” impedance of the signaling traces. Below you’ll find a simple example of a four layer PCB setup.

Layer 1 - Signal (Top Surface)
Prepreg (2116 Dielectric typically; ~4.5 mils thick)
Layer 2 - Copper Plane (Typically for Power Distribution)
Core (Thicker Dielectric than the Prepreg; Width adjusted to make the board thickness ~62 mils)
Layer 3 - Copper Plane (Typically for Ground)
Prepreg (2116 Dielectric typically; ~4.5 mils thick)
Layer 4 - Signal (Bottom Surface)

As mentioned in the above paragraph, the Prepreg actually helps to dictate the static impedance of the trace on the signaling layer/s. The impedance is determined by a combination of factors such as the Er, or dielectric constant, of the Prepreg, and the height of the trace above the copper layer, which is itself determined by the thickness of the Prepreg that is utilized.

When the motherboard designers and printed circuit board manufacturers attempt to find the best layer arrangement, they use something called “field solvers” to create a first pass at gaining the optimal layer arrangement for the targeted trace impedance. If a certain trace need to be, say around 7 mils wide, and the required impedance for the trace needs to be roughly 50 Ohms, the circuit board manufacturer will attempt to idealize their manufacturing process in order to meet these requirements and at the same time, achieve high yields for these impedances.

The impedances for the remaining traces are then solved by the circuit board manufacturer’s own parameters for use with the motherboard. Now, instead of needing a 7 mil trace width with a 50 Ohm impedance, let’s say now that we need a trace with an impedance of 60 Ohms instead. When the circuit board manufacturer runs their software, the solver will tell them that to achieve an impedance of 60 Ohms, a roughly 5 mil wide trace is needed.

If you take a look at the area around the processor socket, and where the bulk of the electrical components for the core voltage power supply are, you’ll tend to notice that there are traces of varying widths and these traces can tend to be spaced out unequally. This is a great example of how the circuit board manufacturers solver adjusts the width of each trace in order to meet the given impedance targets.

Now, if that’s all that was needed, everything would be much easier than it is. When you have several traces near each other that are used as high speed interconnects for the various system busses, certain problems can arise that need to be addressed. If you were only dealing with a single trace running over one of the copper layers, the impedance of the trace would tend to stay near a given level and not vary much, hence the term “static impedance.” However, when you’re talking about several, tightly packed traces some problems can arise. One of the major problems is that you’ll end up with cross-talk. When cross-talk arises, two things tend to happen. First, a high speed edge on one trace can “couple” itself with the signal from a neighboring trace which can cause distortion in that signal, something that obviously needs to be avoided. Secondly, depending on how the trace signal switches in comparison to the neighbor traces, you’ll end up with either something called “even-mode” or “odd-mode” cross-talk. Each of these can be explained rather easily with an example of a three trace system.

In order to figure out if we’re experiencing odd or even-mode cross-talk, we need to pay attention to what the middle trace is doing in comparison to the neighboring traces. If this middle trace is switching from high to low, while the two outside traces switch from low to high, then you have an odd-mode cross-talk situation. Even-mode cross-talk is when identical transitions happen. Here the center trace experiences a transition from low to high, while the neighboring traces also switch from low to high.

In the end, odd-mode and even-mode cross-talk can actually change the effective impedance of a trace. That 60 Ohm trace that you needed has now experienced a change in impedance due to the neighboring traces, and the change itself is dynamic which means the trace impedance will vary depending on the neighboring traces. This is where the simulations once again come into play. These simulations will find the optimal spacing between the various traces and the trace widths in order to deal with the potential for cross-talk. This is the main reason why you’ll notice that some traces are farther apart than others, to keep the impedance target where it should be for the traces. Needless to say, this is a very complex and complicated process.